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MPC954 - LOW VOLTAGE PLL CLOCK DRIVER

Key Features

  • to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC954/D Low Voltage PLL Clock Driver The MPC954 is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 100MHz and output skews of 200ps the MPC954 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and phase jitter. MPC954 • Fully Integrated PLL www.DataSheet4U.com • Output Frequency up to 100MHz LOW VOLTAGE PLL ZERO DELAY BUFFER • Outputs Disable in High Impedance • TSSOP Packaging • 50ps Cycle–to–Cycle Jitter Typical The analog VCC pin of the device also serves as a PLL bypass select pin.