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MPC962308 - 3.3 V Zero Delay Buffer

General Description

The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1.

Select Input Decoding.

Bank B can be tristated if all of the outputs are not required.

Key Features

  • 1:8 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, see Table 2. Available MPC962308 Configurations Multiple low-skew outputs 200 ps max output-output skew 700 ps max device-device skew Two banks of four outputs, output tristate control by two select input.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MPC962308 Rev 3, 08/2004 3.3 V Zero Delay Buffer The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. Features • • • • • • • • • • • • • • • 1:8 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, see Table 2.