MPC962309 Datasheet | Motorola Semiconductor

Features - - - - - - - - - - - - - - MPC962305 MPC962309 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 .. Freescale Semiconductor, Inc... 1:5 LVCMOS zero-delay buffer (MPC962305) 1:9 LVCMOS zero-delay buffer (MPC962309) Zero input-output propagation delay Multiple low-skew outputs 250 ps max output-output skew 700 ps max device-device skew Supports a clock I/O frequency range of 10 MHz to 133 MHz, patible with CPU and PCI bus frequencies Low jitter, 200 ps max cycle-cycle, and patible with Pentium® based systems Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”) 8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin TSSOP package (MPC962309) Single 3.3 V supply Ambient temperature range: - 40°C to +85°C patible with the CY2305, CY23S05, CY2309, CY23S09 Spread spectrum patible DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 948J-01 D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 Functional Description The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3.Select Input Decoding for MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed...