MPC9658 Datasheet | Motorola Semiconductor

Features .. - 1:10 PLL based low-voltage clock generator LOW VOLTAGE 3.3V LVCMOS 1:10 PLL CLOCK GENERATOR Freescale Semiconductor, Inc... Pin and function patible to the MPC958 Functional Description The MPC9658 utilizes PLL technology to frequency lock its outputs FA SUFFIX onto an input reference clock. Normal operation of the MPC9658 requires 32 LEAD LQFP PACKAGE CASE 873A the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency. The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9658 is fully 3.3V patible and requires no external loop filter ponents. The inputs...