Datasheet4U Logo Datasheet4U.com

UPD4481162 - (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM

General Description

The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a 262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

Key Features

  • Low voltage core supply : VDD = 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y) VDD = 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y).
  • Synchronous operation.
  • Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -A75, -C60, -C75) TA =.
  • 40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y).
  • 100 percent bus utilization.
  • Internally self-timed write control.
  • Burst read / write : Interleaved burst and linear burst seque.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
uPD44325092B 36M-BIT QDR II SRAM Renesas
uPD44325182B 36M-BIT QDR II SRAM Renesas
uPD44325362B 36M-BIT QDR II SRAM Renesas
UPD449 2048 x 8-Bit Static CMOS RAM NEC Electronics
UPD4066B Quad Analog Switch / Miltiplexer ETC

Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
UPD4481161 (UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM
UPD4481181 (UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM
UPD4481182 (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM
UPD4481321 (UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM
UPD4481322 (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATA SHEET MOS INTEGRATED CIRCUIT µPD4481162, 4481182, 4481322, 4481362 8M-BIT ZEROSBTM SRAM PIPELINED OPERATION Description The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a 262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).