74AHCT74
74AHCT74 is Dual D-type flip-flop manufactured by NXP Semiconductors.
FEATURES
- ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V
- Balanced propagation delays
- Inputs accepts voltages higher than VCC
- For AHC only: operates with CMOS input levels
- For AHCT only: operates with TTL input levels
- Output capability: standard
- ICC category: flip-flops
- Specified from
- 40 to +85 and +125 °C. DESCRIPTION
The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. 7A. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also plementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. fmax CI CPD QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
74AHC74; 74AHCT74
TYPICAL SYMBOL t PHL/t PLH PARAMETER propagation delay n CP to n Q, n Q n SD, n RD to n Q, n Q max. clock frequency input capacitance power dissipation capacitance CL = 50 p F; f = 1 MHz; notes 1 and 2 CONDITIONS AHC AHCT CL = 15 p F; VCC = 5 V 3.7 3.7 130 VI = VCC or GND 4.0 12 3.3 3.7 100 4.0 16 ns ns MHz p F p F UNIT
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in p F; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLES Table 1 See note 1 INPUT n SD L H L Table 2 n RD H L L See note 1 INPUT n SD H H n RD H H n CP...