74LV4067 Datasheet | NXP Semiconductors

FEATURES - Optimized for low voltage applications: 1.0 to 6.0 V - Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V - Low typ “ON” resistance: - Typical “break before make” built in - Output capability: non-standard - ICC category: MSI 60 W at Vcc - GND = 4.5 V 90 W at Vcc - GND = 3.0 V 145 W at Vcc - GND = 2.0 V DESCRIPTION The 74LV4067 is a low-voltage CMOS device and is pin and function patible with 74HC/HCT4067. The 74LV4067 is an 16-channel analog multiplexer/demultiplexer with four address inputs (So to S3), an active LOW enable input (E), sixteen independent inputs/outputs (Y0 to Y15) and a mon input/output (Z). The 74LV4067 contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to a mon input/output (Z). With E LOW, one of the sixteen switches is selected (low impedance ON- state) by S0 to S3. All unselected switches are in the high impedance OFF-state. With E HIGH, all switches are in the high impedance OFF-state, independent of S0 to S3. The analog inputs/outputs (Y0 to Y15, and Z) can swing between Vcc as a positive limit and GND as a negative limit. Vcc - GND may not exceed 6.0 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns SYMBOL t PZH/t PZL PARAMETER Turn “ON” time E to VOS Sn to VOS Turn “OFF” time E to VOS Sn to VOS Input capacitance Power dissipation capacitance per switch Maximum switch capacitance independent (Y) mon (Z) See Notes 1 and 2 CL = 15 p F RL = 1KW VCC = 3.3 V CONDITIONS TYPICAL 25 27 25 27 3.5 29 5 45 UNIT ns t PHZ/t PLZ CI CPD CS ns p F p F p F NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; CS = max. switch capacitance in p F; VCC = supply voltage in V; ȍ (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING...