74VHCT125 Datasheet PDF - NXP Quad buffer/line driver Specs

74VHCT125 - Quad buffer/line driver

This page provides the datasheet information for the 74VHCT125, a member of the 74VHC125 Quad buffer/line driver family.

Datasheet Summary

Description

The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are speciﬁed in compliance with JEDEC standard JESD7-A.

The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs.

Features

I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC125 operates with CMOS logic levels N The 74VHCT125 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from.
40 °C to +85 °C and from.
40 °C to +125 °C 3. Ordering information Table 1. Ordering informati.

Datasheet Details

Part number	74VHCT125
Manufacturer	NXP
File Size	83.12 KB
Description	Quad buffer/line driver
Datasheet	74VHCT125 Datasheet
Additional preview pages of the 74VHCT125 datasheet.

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Full PDF Text Transcription

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74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 02 — 13 October 2009 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2.

Published: Aug 5, 2015 |