Datasheet Details
| Part number | HEF4510B |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 135.14 KB |
| Description | BCD up/down counter |
| Datasheet | HEF4510B_PhilipsSemiconductors.pdf |
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Overview: INTEGRATED CIRCUITS DATA SHEET For a plete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4510B.
| Part number | HEF4510B |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 135.14 KB |
| Description | BCD up/down counter |
| Datasheet | HEF4510B_PhilipsSemiconductors.pdf |
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The HEF4510B is an edge-triggered synchronous up/down BCD counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR).
Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW.
With PL LOW, the counter changes on the LOW to HIGH transition of CP if CE is LOW.
| Part Number | Description |
|---|---|
| HEF4511B | BCD to 7-segment latch/decoder/driver |
| HEF4512B | 8-input multiplexer with 3-state output |
| HEF4514B | 1-of-16 decoder/demultiplexer with input latches |
| HEF4515B | 1-of-16 decoder/demultiplexer with input latches |
| HEF4516B | Binary up/down counter |
| HEF4517B | Dual 64-bit static shift register |
| HEF4518B | Dual BCD counter |
| HEF4519B | Quadruple 2-input multiplexer |
| HEF4502B | Strobed hex inverter/buffer |
| HEF4505B | 64-bit/ 1-bit per word random access read/write memory |