NXP Semiconductors HEF4510B
The HEF4510B is an edge-triggered synchronous up/down BCD counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). With PL LOW, the counter changes on the LOW to HIGH transition of CP if CE is LOW. When counting up, TC is LOW when O0 and O3 are HIGH and CE is LOW.
| Part No. |
HEF4510B |
| Datasheet |
HEF4510B
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| Manufacturer |
 NXP Semiconductors |
| Description |
BCD up/down counter |
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DESCRIPTION
Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting down, TC is LOW when O0 to O3 and CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions. HEF4510B MSI Fig.1 Functional diagram. PINNING HEF4510BP(N): HEF4510BD(F): HEF4510BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America UP/DN MR TC O0 to O3 PL P0 to P3 CE CP parallel load input (active HIGH) parallel inputs count enable input (active LOW) clock pulse input (LOW to HIGH, edge triggered) up/down count control input master reset input terminal count output (active LOW) parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications Fig.2 Pinning diagram. January 1995 2 Philips Semiconductors Product specification BCD up/down counter HEF4510B MSI Fig.3 Logic diagram (continued in Fig.4).
