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HEF4518B - Dual BCD counter

General Description

T he HEF4518B is a dual 4-bit internally synchronous BCD counter.

The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4518B MSI Dual BCD counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Dual BCD counter DESCRIPTION T he HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR).