HEF4518B Description
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has two clock inputs (CP0 and CP1 ), buffered outputs from all four bit positions (O0 to O3) and an asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to LOW transition of the CP1 input if CP0 is LOW.
HEF4518B Key Features
- Wide supply voltage range from 3.0 V to 15.0 V
- CMOS low power dissipation
- High noise immunity
- Tolerant of slow clock rise and fall times
- Fully static operation
- 5 V, 10 V, and 15 V parametric ratings
- Standardized symmetrical output characteristics
- plies with JEDEC standard JESD 13-B
- ESD protection
- HBM JESD22-A114F exceeds 2000 V