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PCK2510S - 50-150 MHz 1:10 SDRAM clock driver

General Description

The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Key Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

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Other Datasheets by NXP Semiconductors

Part Number Description
PCK2510SA 50-150 MHz 1:10 SDRAM clock driver
PCK2510SL 50-150 MHz 1:10 SDRAM clock driver
PCK2509S 50-150 MHz 1:9 SDRAM clock driver
PCK2509SA 50-150 MHz 1:9 SDRAM clock driver
PCK2509SL 50-150 MHz 1:9 SDRAM clock driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS PCK2510S 50–150 MHz 1:10 SDRAM clock driver Product specification 1999 Dec 13 Philips Semiconductors Philips Semiconductors Product specification 50–150 MHz 1:10 SDRAM clock driver PCK2510S FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the PCK2510S does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.