PCK940L Datasheet | NXP Semiconductors

description The PCK940L is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS patible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS patible and feature the drive strength to drive 50 Ω series or parallel terminated transmission lines. With output-to-output skews of 150 ps, the PCK940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. With a low output impedance of approximately 20 Ω, in both the HIGH and LOW logic states, the output buffers of the PCK940L are ideal for driving series terminated transmission lines. With an output impedance of 20 Ω, the PCK940L has the capability of driving two series terminated transmission lines from each output. This gives the PCK940L an effective fan-out of 1 : 36. If a lower output impedance is desired, please see the PCK942C data sheet. The differential LVPECL inputs of the PCK940L allow the device to interface directly with a LVPECL fan-out buffer like the PCKEP111 to build very wide clock fan-out trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLKSEL pin will select the LVCMOS level clock input. All inputs of the PCK940L have internal pull-up/pull-down resistors so they can be left open if unused. The PCK940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs, as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP...