PCK9447 Datasheet | NXP Semiconductors

description The PCK9447 is a 3.3 V or 2.5 V patible, 1 : 9 clock fan-out buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz, and output skews less than 150 ps, the device meets the needs of most demanding clock applications. The PCK9447 is specifically designed to distribute LVCMOS patible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with near zero skew. The output buffers support driving of 50 Ω terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS patible clock inputs are available, providing support of redundant clock source systems. The PCK9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic LOW state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of - 40 °C to +85 °C. The PCK9447 is pin and function patible but performance-enhanced to the PCK947. 2. Features s s s s s s s s s s s 9 LVCMOS patible clock outputs 2 selectable, LVCMOS patible inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps Synchronous output stop in logic LOW state eliminates output runt pulses High-impedance output control 3.3 V or 2.5 V power supply Drives up to 18 series terminated clock lines Tamb = - 40 °C to +85 °C Available in LQFP32 package Supports clock distribution in networking, telemunications and puter applications s Pin and function patible to PCK947 Philips Semiconductors 3.3 V/2.5 V 1 : 9 LVCMOS clock fan-out buffer 3. Ordering information Table 1: Ordering...