PCK9456 Datasheet | NXP Semiconductors

description The PCK9456 is a 2.5 V and 3.3 V patible 1 : 10 clock distribution buffer designed for low voltage mid-range to high-performance telemunications, networking and puting applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed voltage applications. The PCK9456 offers 10 low-skew outputs and a differential LVPECL clock input. The outputs are configurable and support 1 : 1 and 1 : 2 output to input frequency ratios. The PCK9456 is specified for the extended temperature range of - 40 °C to +85 °C. .. 2. Features I I I I I I I I I I Configurable 10 outputs LVCMOS clock distribution buffer patible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock frequency up to 250 MHz Designed for mid-range to high performance telemunications, networking and puter applications Supports high performance differential clocking applications Maximum output skew of 200 ps (150 ps within one bank) Selectable output configurations per output bank 3-stateable outputs Available in LQFP32 package Ambient operating temperature of - 40 °C to +85 °C 3. Ordering information Table 1. Ordering information Package Name PCK9456BD LQFP32 Description plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm Version SOT358-1 Type number Philips Semiconductors 2.5 V and 3.3 V LVCMOS clock fan-out buffer 4. Functional diagram PCLK 25 kΩ bank A CLK 0 QA0 QA1 PCLK 25 kΩ 0.5VCC CLK ÷ 2 1 QA2 bank B .. QB0 QB1 1 QB2 FSELA 25 kΩ bank C 0 QC0 QC1 QC2 QC3 FSELB 25 kΩ FSELC 25 kΩ MR/OE 25 kΩ 002aab862 Fig 1. Functional diagram of PCK9456 PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev....