PCK9446 Datasheet | NXP Semiconductors

description The PCK9446 is a 2.5 V and 3.3 V patible 1 : 10 clock distribution buffer designed for low-voltage mid-range to high-performance tele, networking and puting applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The PCK9446 offers 10 low skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1 : 1 and 1 : 2 output to input frequency ratios. The PCK9446 is specified for the extended temperature range of - 40 °C to +85 °C. The PCK9446 is a full static design supporting clock frequencies up to 250 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS patible clock inputs are available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The PCK9446 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic HIGH state). Asserting OE will enable the outputs. All inputs accept LVCMOS signals while the outputs provide LVCMOS patible levels with the capability to drive terminated 50 Ω transmission lines. Please refer to the PCK9456 specification for a 1 : 10 mixed voltage buffer with LVPECL patible inputs. For series terminated transmission lines, each of the PCK9446 outputs can drive one or two traces giving the devices an effective fan-out of 1 : 20. The device is packaged in a 32-lead LQFP package which has a 7 mm × 7 mm body size with a conservative 0.8 mm pin spacing. 2. Features I I I I I I I I I I Configurable 10 outputs LVCMOS clock distribution buffer patible to single, dual and mixed 3.3 V/2.5 V voltage supply Wide range output clock...