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PCK946 - Low voltage 1 : 10 CMOS clock driver

General Description

The PCK946 is a low voltage CMOS 1 : 10 clock buffer.

The 10 outputs can be configured into a standard fan-out buffer or into 1× and 1⁄2× combinations.

The ten outputs were designed and optimized to drive 50 Ω series or parallel terminated transmission lines.

Key Features

  • selectability to allow the user to select the ratio of 1× outputs to 1⁄2× outputs. Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_SEL input pulled HIGH, the TCLK1 input is selected. All of the control inputs are LVCMOS/LVTTL compatible. The DSELn pins choose between 1× and 1⁄2× outputs. A LOW on the DSELn pins will select the 1.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PCK946 Low voltage 1 : 10 CMOS clock driver Rev. 01 — 13 December 2005 www.DataSheet4U.com Product data sheet 1. General description The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured into a standard fan-out buffer or into 1× and 1⁄2× combinations. The ten outputs were designed and optimized to drive 50 Ω series or parallel terminated transmission lines. With output-to-output skews of 350 ps, the PCK946 is ideal as a clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. With an output impedance of approximately 7 Ω, in both the HIGH and LOW logic states, the output buffers of the PCK946 are ideal for driving series terminated transmission lines.