PCK946 Datasheet | NXP Semiconductors

description The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured into a standard fan-out buffer or into 1× and 1⁄2× binations. The ten outputs were designed and optimized to drive 50 Ω series or parallel terminated transmission lines. With output-to-output skews of 350 ps, the PCK946 is ideal as a clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. With an output impedance of approximately 7 Ω, in both the HIGH and LOW logic states, the output buffers of the PCK946 are ideal for driving series terminated transmission lines. More specifically, each of the 10 PCK946 outputs can drive two series terminated transmission lines. With this capability, the PCK946 has an effective fan-out of 1 : 20 in applications using point-to-point distribution schemes. The PCK946 has the capability of generating 1× and 1⁄2× signals from a 1× source. The design is fully static; the signals are generated and re-timed inside the chip to ensure minimal skew between the 1× and 1⁄2× signals. The device features selectability to allow the user to select the ratio of 1× outputs to 1⁄2× outputs. Two independent LVCMOS/LVTTL patible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_SEL input pulled HIGH, the TCLK1 input is selected. All of the control inputs are LVCMOS/LVTTL patible. The DSELn pins choose between 1× and 1⁄2× outputs. A LOW on the DSELn pins will select the 1× output. The MR/OE input will reset the internal flip-flops and 3-state the outputs when it is forced HIGH. The PCK946 is fully 3.3 V patible. The 32-lead LQFP package was chosen to optimize performance, board space, and cost of the device. The 32-lead LQFP package has a 7 mm × 7 mm body size with a conservative 0.8 mm pin spacing. 2. Features s s s s s s s 2 selectable LVCMOS/LVTTL clock inputs 350 ps...