PCK953 Datasheet | NXP Semiconductors

DESCRIPTION The PCK953 is a 3.3 V patible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter. The PCK953 has a differential LVPECL reference input, along with an external feedback input. These features make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V patible and requires no external loop filter ponents. All control inputs accept LVCMOS or LVTTL patible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 Ω transmission lines. For series terminated 50 Ω lines, each of the PCK953 outputs can drive two traces, giving the device an effective fanout of 1:18. The device is packaged in a 7 × 7 mm 32-lead LQFP package to provide the optimum bination of board density and performance. PIN CONFIGURATION 32 VCO_SEL 31 BYPASS 30 PLL_EN 29 GNDO 25 GNDO 24 Q1 23 VCCO 22 Q2 21 GNDO 20 Q3 19 VCCO 18 Q4 17 GNDO MR/OE 10 Q7 12 GNDO 13 Q6 14 V CCO 15 V CCO 11 Q5 16 9 27 V CCO 28 QFB VCCA FB_CLK NC NC NC NC GNDI PECL_CLK 1 2 3 4 5 6 7 8 PECL_CLK 26 Q0 SW00625 FEATURES - Fully integrated PLL - Output frequency up to 125 MHz in PLL mode - Outputs disable in high impedance - LQFP packaging - 55 ps cycle-to-cycle jitter typical - 9 m A quiescent current, ICCA, typical - 60 ps static phase offset typical - Less than 10 µA quiescent current, l CCO, typical ORDERING INFORMATION PACKAGES plastic low profile quad flat package; 32 leads TEMPERATURE RANGE 0 to +70°C ORDER CODE PCK953BD DRAWING NUMBER SOT358-1 LOGIC DIAGRAM QFB PECL_CLK PECL_CLK PHASE DETECTOR FB_CLK LPF VCO...