Description
The 1Gb Double-Data-Rate-3 (DDR3/L) B-die DRAMs is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices.
Features
- and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067/+0.1V power supply and are available in BGA packages. DCC Version 1.1
01 / 2014
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NT5CB64M16DP Datasheet
