Description
The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices.
Features
- JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
- Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
- Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
- Signal Integrity - Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.
NT5CB64M16FP Datasheet
