NT5CB64M16GP Overview
Key Features
- Basis DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
- Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
- Power Saving Mode
- Partial Array Self Refresh (PASR)1 - Power Down Mode
- Signal Integrity
