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NT5CC512M8EQ - Commercial and Industrial DDR3 4Gb SDRAM

Key Features

  • Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
  • Signal Synchroniza.

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Datasheet Details

Part number NT5CC512M8EQ
Manufacturer Nanya
File Size 3.35 MB
Description Commercial and Industrial DDR3 4Gb SDRAM
Datasheet download datasheet NT5CC512M8EQ Datasheet

Full PDF Text Transcription for NT5CC512M8EQ (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NT5CC512M8EQ. For precise diagrams, and layout, please refer to the original PDF.

DDR3-4Gb E-Die NT5CB(C)512M8EQ/NT5CB(C)256M16ER Commercial and Industrial DDR3(L) 4Gb SDRAM Features  Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Cloc...

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 Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 5 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1352 for

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