• Part: 54AC158
  • Description: Quad 2-Input Multiplexer
  • Manufacturer: National Semiconductor
  • Size: 155.85 KB
Download 54AC158 Datasheet PDF
National Semiconductor
54AC158
54AC158 is Quad 2-Input Multiplexer manufactured by National Semiconductor.
.. 54AC58 - 54ACT158 Quad 2-Input Multiplexer July 1998 - 54ACT158 Quad 2-Input Multiplexer General Description The ’AC/’ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the mon Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The ’AC/’ACT158 can also be used as a function generator. n Outputs source/sink 24 m A n ’ACT158 has TTL-patible inputs n Standard Microcircuit Drawing (SMD) - ’AC158: 5962-89729 - ’ACT158: 5962-88755 Features n ICC reduced by 50% Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100273-1 IEE/IEC DS100273-3 Pin Assignment for LCC DS100273-2 DS100273-4 Pin Names I0a- I0d I1a- I 1d E S Za- Zd Description Source 0 Data Inputs Source 1 Data Inputs Enable Input Select Input Inverted Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100273 .national. Functional Description The ’AC/’ACT158 quad 2-input multiplexer selects four bits of data from two sources under the control of a mon Select input (S) and presents the data in inverted form at the four outputs. The Enable input (E) is active-LOW. When E is HIGH, all of the outputs (Z) are forced HIGH regardless of all other inputs. The ’AC/’ACT158 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. A mon use of the ’AC/’ACT158 is the moving of data from two groups of registers to four mon output busses. The particular register from which the data es is determined by the state of the Select input. A less obvious use is as a function generator. The ’AC/’ACT158 can generate four functions of two variables with one variable mon. This is useful for implementing gating functions. Truth Table Inputs E H L L L L S X L L H H I0 X L H X X I1 X X X L H Outputs...