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DP8481 - TTL to 10k ECL Level Translator with Latch

Description

This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels

Features

  • Y Y Y Y Y 16-pin flat-pack or DIP ECL control inputs CS provided for wire ORing of output bus 10k ECL I O compatible 3 0 ns typical propagation delay Logic and Connection Diagram Dual-In-Line Package Truth Table D H L X X Q L H Q L STR L L H X CS H H H L H e high level (most positive) L e low level (most negative) X e don’t care Order Number DP8481F DP8481J or DP8481N See NS Package F16B J16A or N16A TL F 5862.
  • 1 Top View C1995 National Semiconductor Corporation TL F 5862 RRD-.

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Datasheet Details

Part number DP8481
Manufacturer National Semiconductor
File Size 110.37 KB
Description TTL to 10k ECL Level Translator with Latch
Datasheet download datasheet DP8481 Datasheet
Additional preview pages of the DP8481 datasheet.

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Full PDF Text Transcription

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DP8481 TTL to 10k ECL Level Translator with Latch June 1986 DP8481 TTL to 10k ECL Level Translator with Latch General Description This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels Features Y Y Y Y Y 16-pin flat-pack or DIP ECL control inputs CS provided for wire ORing of output bus 10k ECL I O compatible 3 0 ns typical propagation delay Logic and Connection Diagram Dual-In-Line Package Truth Table D H L X X Q L H Q L STR L L H X CS H H H L H e high level (most positive) L e low level (most negative) X e don’t care Order Number DP8481F DP8481J or DP8481N See NS Package F16B J16A or N16A TL F 5862 – 1 Top View C1995
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