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DP8483 - TTL to 100k ECL Level Translator with Latch

Description

This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels

Features

  • Y Y Y Y Y 16-pin DIP or S O ECL control inputs CS provided for wire ORing of output bus 100k ECL I O compatible 3 0 ns typical propagation delay Logic and Connection Diagram Dual-In-Line Package Truth Table D H L X X Q L H Q L STR L L H X CS H H H L H e high level (most positive) L e low level (most negative) X e don’t care Order Number DP8483J DP8483M or DP8483N See NS Package Number J16A M16B or N16A TL F 5864.
  • 1 Top View C1995 National Semiconductor Corporation TL F 5864.

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Datasheet Details

Part number DP8483
Manufacturer National Semiconductor
File Size 118.06 KB
Description TTL to 100k ECL Level Translator with Latch
Datasheet download datasheet DP8483 Datasheet
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Full PDF Text Transcription

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DP8483 TTL to 100k ECL Level Translator with Latch April 1990 DP8483 TTL to 100k ECL Level Translator with Latch General Description This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels Features Y Y Y Y Y 16-pin DIP or S O ECL control inputs CS provided for wire ORing of output bus 100k ECL I O compatible 3 0 ns typical propagation delay Logic and Connection Diagram Dual-In-Line Package Truth Table D H L X X Q L H Q L STR L L H X CS H H H L H e high level (most positive) L e low level (most negative) X e don’t care Order Number DP8483J DP8483M or DP8483N See NS Package Number J16A M16B or N16A TL F 5864 – 1 Top Vi
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