DS90CF561 Datasheet PDF - National Semiconductor LVDS 18-Bit Color Flat Panel Display Link Specs

DS90CF561 - LVDS 18-Bit Color Flat Panel Display Link

Datasheet Summary

Description

The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Features

n n n n n n n n n Up to 105 Megabyte/sec bandwidth Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI Low power CMOS design Power down mode PLL requires no external components Low profile 48-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Block Diagrams DS90CF561 DS90CF562 DS012485-26 DS012485-1 Order Number DS90CF561MTD See NS Package Number MTD48 Order Number DS90CF562MTD See NS Package Number MTD48 TRI-STATE ® is a register.

Datasheet Details

Part number	DS90CF561
Manufacturer	National Semiconductor
File Size	244.85 KB
Description	LVDS 18-Bit Color Flat Panel Display Link
Datasheet	DS90CF561 Datasheet
Additional preview pages of the DS90CF561 datasheet.

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Full PDF Text Transcription

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DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link July 1997 DS90CF561/DS90CF562 LVDS 18-Bit Color Flat Panel Display (FPD) Link General Description The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel.

Published: Mar 30, 2005 |