DS90CF563 Datasheet PDF - National Semiconductor LVDS 18-Bit Color Flat Panel Display Link Specs

DS90CF563 - LVDS 18-Bit Color Flat Panel Display Link

Datasheet Summary

Description

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Features

n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 171 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design ( < 550 mW typ) Power-down mode saves power ( < 0.25 mW) PLL requires no external components Low profile 48-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Single pixel per clock XGA (1024 x 768) Supports VGA, SVGA, XGA and higher 1.3 Gbps throughput Block Diagrams DS90CF563 DS90.

Datasheet Details

Part number	DS90CF563
Manufacturer	National Semiconductor
File Size	287.80 KB
Description	LVDS 18-Bit Color Flat Panel Display Link
Datasheet	DS90CF563 Datasheet
Additional preview pages of the DS90CF563 datasheet.

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Full PDF Text Transcription

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DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz July 1997 DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel.

Published: Mar 30, 2005 |