DP83861 Datasheet | National Semiconductor

Description Features The DP83861 is a full featured Physical Layer transceiver s 100BASE-TX and 1000BASE-T pliant with integrated PMD sublayers to support 10BASE-T, s Fully pliant to IEEE 802.3u 100BASE-TX and IEEE 100BASE-TX and 1000BASE-T Ethernet protocols. 802.3z/ab 1000BASE-T specifications. Fully integrated and fully pliant ANSI X3.T12 PMD physical sublayer The DP83861 uses state of the art 0.18 µm , 1.8 V/3.3 V that includes adaptive equalization and Baseline Wan CMOS technology, fabricated at National Semiconductor’s der pensation South Portland Maine facility. s 10BASE-T patible The DP83861 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to s IEEE 802.3u Auto-Negotiation and Parallel Detection Twisted Pair media via an external transformer. This device - Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, interfaces directly to the MAC layer through the IEEE and 10 Mb/s Full Duplex and Half Duplex devices 802.3u Standard Media Independent Interface (MII) or the s Interoperates with first generation 1000BASE-T Physical IEEE 802.3z Gigabit Media Independent Interface (GMII). layer transceivers s 3.3V MAC interfaces: Applications - IEEE 802.3u MII The DP83861 fits applications in: - IEEE 802.3z GMII s 10/100/1000 Mb/s capable node cards s LED support: Link, Speed, Activity, Collision, TX and RX s Switches with 10/100/1000 Mb/s capable ports s Supports 125 MHz or 25 MHz reference clock s High speed uplink ports (backbone) s Requires only one 1.8 V and one 3.3 V supply s Supports MDIX at 10, 100, and 1000 Mb/s s Supports JTAG (IEEE1149.1) s Dissipates 1 watt in 10/100 Mb/s mode s Programmable Interrupts s 208-pin PQFP package .. System Diagram MAGNETICS 10BASE-T 100BASE-TX RJ-45 1000BASE-T 10/100/1000Mb/s Ethernet Physical Layer MII/GMII DP83820 10/100/1000Mb/s ETHERNET MAC STATUS LEDs 125 MHz or 25 MHz CLOCK PHYTER® is a registered trademark of National Semiconductor Corporation. © 2001 National...