DP8481 Datasheet | National Semiconductor

Description This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels Features Y Y Y Y Y 16-pin flat-pack or DIP ECL control inputs CS provided for wire ORing of output bus 10k ECL I O patible 3 0 ns typical propagation delay Logic and Connection Diagram Dual-In-Line Package Truth Table D H L X X Q L H Q L STR L L H X CS H H H L H e high level (most positive) L e low level (most negative) X e don’t care Order Number DP8481F DP8481J or DP8481N See NS Package F16B J16A or N16A TL F 5862 - 1 Top View C1995 National Semiconductor Corporation TL F 5862 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications VEE Supply Voltage VCC Supply Voltage Input Voltage (ECL) Input Voltage (TTL) Output Current Maximum Power Dissipation at 25 C Molded Package Storage Temperature Derate molded package 11 8 m W C above 25 C Remended Operating Conditions VEE Supply Voltage VCC Supply Voltage TA Ambient Temperature b 5 2V g 10% 5 0V g 10% 0 C to 75 C b 8V 7V GND to VEE b 1V to 5 5V 50 m A 1476 m W b 65 C to a 150 C Electrical Characteristics (TTL Logic) (Notes 2 and 3) Symbol VIL VIH IIL IIH VCLAMP ICC Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Input Clamp Voltage Supply Current VIN e 0 5V VIN e 2 5V IIN eb12 m A VCC e 5 5V 20 b 25 b 200 Conditions Min Typ Max 08 Units V V m A m A V m A 10 b0 9 40 b1 2 Electrical Characteristics (ECL Logic) (Notes 2 and 3) Symbol VIL Parameter Input Low Voltage Conditions VEE eb5 2V TA 0C 25 C 75 C 0C 25 C 75 C Min b 1870 b 1850 b 1830 b 1145 b 1105 b 1045 Typ Max b 1490 b 1475 b 1450 b 840 b 810 b 720 Units m...