DS90CF561 Datasheet | National Semiconductor

Description The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF562 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 105 Megabytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n n n n n n n n n Up to 105 Megabyte/sec bandwidth Narrow bus reduces cable size and cost 290 m V swing LVDS devices for low EMI Low power CMOS design Power down mode PLL requires no external ponents Low profile 48-lead TSSOP package Falling edge data strobe patible with TIA/EIA-644 LVDS standard Block Diagrams DS90CF561 DS90CF562 DS012485-26 DS012485-1 Order Number DS90CF561MTD See NS Package Number MTD48 Order Number DS90CF562MTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS012485 .national. Block Diagrams (Continued) Application DS012485-2 Connection Diagrams DS012485-3 DS90CF562 DS012485-4 .national. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) - 0.3V to +6V CMOS/TTL Input Voltage - 0.3V to (VCC + 0.3V) CMOS/TTL Ouput Voltage - 0.3V to (VCC +...