Description
These dual N & P
Channel logic level enhancement mode field
effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology, this very high density process is especially tailored to minimize on
state resistance.
Features
- N.
- Ch 0.22 A, 0.25 V.
- RDS(ON) = 4.0 W @ VGS = 4.5 V.
- RDS(ON) = 5.0 W @ VGS = 2.7 V.
- P.
- Ch.
- 0.14 A,.
- 25 V.
- RDS(ON) = 10 W @ VGS =.
- 4.5 V.
- RDS(ON) = 13 W @ VGS =.
- 2.7 V.
- Very Small Package Outline SC70.
- 6.
- Very Low Level Gate Drive Requirements Allowing Direct
Operation in 3 V Circuits (VGS(th) < 1.5 V).
- Gate.
- Source Zener for ESD Ruggedness (>6 kV Human Bod.
FDG6320C Datasheet
