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NB4N527S - Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator

General Description

Pin Name I/O Description 1 VTD1

Internal 50 W termination pin for D1.

Noninverted differential clock/data D1 input (Note 1).

Inverted differential clock/data D1 input (Note 1).

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Datasheet Details

Part number NB4N527S
Manufacturer onsemi
File Size 175.99 KB
Description Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator
Datasheet download datasheet NB4N527S Datasheet

Full PDF Text Transcription for NB4N527S (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NB4N527S. For precise diagrams, and layout, please refer to the original PDF.

NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination NB4N527S is a clock or data Receiver/Driver/Buffer/Transl...

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Termination NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.5 GHz, respectively. The NB4N527S has a wide input common mode range of GND + 50 mV to VCC − 50 mV combined with two 50 W internal termination resistors is ideal for translating differential or single−ended data or clock signals to 350 mV typical LVDS output levels without us

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