NB4N527S - Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator

Datasheet Summary

Description

Pin Name I/O Description 1 VTD1

Internal 50 W termination pin for D1.

Noninverted differential clock/data D1 input (Note 1).

Inverted differential clock/data D1 input (Note 1).

ON Semiconductor

📥 Download Datasheet

Datasheet Details

Part number	NB4N527S
Manufacturer	ON Semiconductor
File Size	175.99 KB
Description	Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator
Datasheet	NB4N527S Datasheet
Additional preview pages of the NB4N527S datasheet.

📁 Similar Datasheet

NB4148 - Small Signal Fast Switching Bridge (World Internation Limited)

Other Datasheets by ON Semiconductor

NB4N507A - PECL Clock Synthesizer
NB4N111K - Clock Fanout Buffer
NB4N1158 - Link Replicator
NB4N11M - Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
NB4N11S - 3.3V 1:2 AnyLevel Input to LVDS Fanout Buffer /Translator
NB4N121K - 3.3V Differential 1:21 Differential Fanout Clock Driver
NB4N316M - AnyLevel Receiver to CML Driver/Translator
NB4N441 - 3.3V Serial Input MultiProtocol PLL Clock Synthesizer

Full PDF Text Transcription

Click to expand full text

NB4N527S 3.3V, 2.5Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.5 GHz, respectively. The NB4N527S has a wide input common mode range of GND + 50 mV to VCC − 50 mV combined with two 50 W internal termination resistors is ideal for translating differential or single−ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components (Figure 6).

Published: Jan 12, 2007 |