NB7V32M - Clock Divider

Description

asynchronous reset.

The differential Clock inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML and LVDS logic levels.

The NB7V32M produces a B2 output copy of an input Clock operating up to 10 GHz with minimal jitter.

Features

Maximum Input Clock Frequency > 10 GHz, typical.
Random Clock Jitter < 0.8 ps RMS.
200 ps Typical Propagation Delay.
35 ps Typical Rise and Fall Times.
Differential CML Outputs, 400 mV Peak.
to.
Peak, Typical.
Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V.
Internal 50 W Input Termination Resistors.
QFN.
16 Package, 3 mm x 3 mm.
40°C to +85°C Ambient Operating Temperature.

ON Semiconductor

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Datasheet Details

Part number	NB7V32M
Manufacturer	ON Semiconductor
File Size	231.42 KB
Description	Clock Divider
Datasheet	NB7V32M Datasheet
Additional preview pages of the NB7V32M datasheet.

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Full PDF Text Transcription

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1.8 V/2.5 V, 10 GHz ÷2 Clock Divider with CML Outputs Multi−Level Inputs w/ Internal Termination NB7V32M Description The NB7V32M is a differential B2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a B2 output copy of an input Clock operating up to 10 GHz with minimal jitter. The RESET Pin is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M’s in a system. The 16 mA differential CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated with 50 W to VCC . The NB7V32M is the 1.

Published: Feb 11, 2010 |