NB7V586M Description
Multi−Level Inputs w/ Internal Termination The NB7V586M is a differential 1−to−6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels (see Figure 12). The INx/INx inputs and core logic are powered with a 1.8 V supply.
NB7V586M Key Features
- For additional marking information, refer to Application Note AND8002/D
- Rev. 0
NB7V586M Applications
- For additional marking information, refer to Application Note AND8002/D