Download P3P623S00B Datasheet PDF
P3P623S00B page 2
Page 2
P3P623S00B page 3
Page 3

P3P623S00B Description

P3P623S00B/E is a versatile, 3.3 V Zero−delay buffer designed to distribute Timing−Safe clocks with Peak EMI reduction. P3P623S00B is an eight−pin version, accepts one reference input and drives out one low−skew Timing−Safe clock. P3P623S00E accepts one reference input and drives out eight low−skew Timing−Safe clocks.

P3P623S00B Key Features

  • Clock Distribution with Timing-Safe Peak EMI Reduction
  • Input Frequency Range: 20 MHz
  • 50 MHz
  • 2 Different Spread Selection Options
  • Spread Spectrum can be Turned ON/OFF
  • External Input-Output Delay Control Option
  • Supply Voltage: 3.3 V ± 0.3 V
  • P3P623S00B: 8 Pin SOIC
  • The First True Drop-in Solution
  • These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS