P4C1258 Datasheet | PYRAMID

FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) - 15/20/25/35 ns (mercial/Industrial) Low Power Single 5V±10% Power Supply Data Retention with 2.0V Supply Three-State Outputs TTL/CMOS patible Outputs Fully TTL patible Inputs Standard Pinout (JEDEC Approved) - 24-Pin 300 mil DIP, SOJ DESCRIPTION The P4C1258 is a 262,144-bit ultra high speed static RAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-patible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. The P4C1258 is available in a 24-pin 300 mil DIP or SOJ...