Datasheet Summary
CCD Delay Line Series
NTSC CCD Video Signal Delay Element
Overview
The MN3880S is a CCD signal delay element for video signal processing applications. It contains such ponents as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3880S samples the input using the supplied clock signal with a frequency of 7.15909 MHz, twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines.
Pin Assignment
VBIASC VOC N.C. VDD
- VBB N.C.
1 2 3 4 5 6 7 8
16 15 14 13 12...