MN3881S
Overview
The MN3881S is a CCD signal delay element for video signal processing applications. It contains such ponents as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch pin is grounded, the MN3881S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output.
Pin Assignment
VBIASC VOC N.C. VDD
- VBB N.C. VOY VBIASY
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VINC N.C. N.C. XI VSS SW N.C. VINY
Features
Single 4.9 V power supply Single chip bining luminance signal delay element and delay element for color signal converted to low frequency.
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