Overview: CCD Delay Line Series MN3883S
Full Multi-PAL-patible CCD Video Signal Delay Element
Overview
The MN3883S is a CCD signal delay element for video signal processing applications. It contains such ponents as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch input is "H" level, the MN3883S samples the input using the supplied clock signal with a frequency 7.15909 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "M" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "L" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output. Pin Assignment VBIASC VOC N.C. VDD –VBB N.C. VOY VBIASY 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINC N.C. N.C. XI VSS SW N.C.
