PLL52C63-01 Datasheet | PhaseLink

Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers Features n Generates all clock frequencies for Pentium (II), AMD and Cyrix system requiring multiple CPU clocks. n Supports up to16 Synchronous CPU clocks (4 CPU and 12 SDRAM) and 7 Synchronous PCI BUS clocks. n Two 14.318Mhz reference clocks and one 2.5V IOAPIC n One 24Mhz floppy clock and one 48Mhz USB clock. n Power management control pins to stop CPU, SDRAM or PCI BUS clocks. n Supports 2-wire I2C serial bus interface. n 50% duty cycle with low jitter n Mixed voltage support from 3.0 to 5V or (VDDq2=2.5V) n Available in 300mil 48 pin SSOP. PIN INFORMATION FREQUENCY SELECTION (MHz) F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 F0 PCLK/SDRAM 0 1 0 1 0 1 0 1 50 100 83.3 68.5 55 75 60 66.6 BCLK 25 50 41.6 34.2 27.5 37.5 30 33.3 Note: F2,F1,F0 and MODE are se lecta ble only dur ing power- on. They are HIGH by de fault and LOW when 10K Ω Pull down is at tached. I/O MODE CONFIGURATION MODE 1 (OUT PUT) 0 (IN PUT) PIN15 BCLK5 PCISTP PIN46 REF1 CPUSTP BLOCK DIAGRAM 45437 Warm Springs Blvd., Fre mont, Cali for nia 94539, TEL 510- 492- 0990 FAX 510- 492- 0991 9704.Rev.1C Page 1 SIGNAL DESCRIPTIONS NAME VDD VDDq2 VSS XIN XOUT BCLK_F/F1- BCLK_0/F2- 48MHZ/F0- BCLK_F, BCLK(0:5) PCLK(0:3) SDRAM(0:11) SDATA SCLK BCLK5//PCISTP REF1//CPUSTP 48MHZ/F0- 24MHZ/MODE- REF(0:1) IOAPIC PIN NUM BER 1,6,14, 19,30,36 42,48 3,9,16,22 27,33,39,45 4 5 7,8,26 7,8,10,11 12,13,15 44,43,41,40 38,37,35,34 32,31,29,28 21,20,18,17 23 24 15 46 26 25 2,46 47 PIN TYPE P P P I O B Power sup ply (3V ~ 5V) Power sup ply 2.5V- 5V Ground 14.318Mhz crys tal in put to be con nected to one end of the crys tal. This in put can also be con nected di rectly to other avail able source of 14.318Mhz from the PC board. 14.318Mhz crys tal out put At power- up, these pins are in put pins and will de ter mine the CPU clock fre quency (see Fre quency Se lec tion Ta ble). Af ter in put sam pling, these pins will gen er ate out put clocks. PCI Bus clocks...