74F199 Datasheet | Philips Semiconductors

FEATURES - Buffered clock and control inputs - Shift right and parallel load capability - Fully synchronous data transfers - J-K(D) inputs to first stage - Clock enable for hold (do nothing) mode - Asynchronous Master Reset DESCRIPTION The 74F199 is an 8-bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. The device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel- to-serial data transfers at very high speeds. The 74F199 operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2 following each Low-to-High clock transition. The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications. The device appears as eight mon clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0- D7) is transferred to the respective Q0- Q7 outputs. All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F199 utilizes edge-triggered, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs for logic operation, other than the setup and hold time requirements. A Low on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously forcing all bit positions to a Low state. PIN CONFIGURATION K 1 J D0 Q0 D1 Q1 D2 Q2 D3 2 3 4 5 6 7 8 9 24 VCC 23 PE 22 D7 21 Q7 20 D6 19 Q6 18 D5 17 Q5 16 D4 15 Q4 14 MR 13 CP Q3 10 CE 11 GND 12 SF00152 TYPE 74F199 TYPICAL f MAX 95MHz TYPICAL SUPPLY CURRENT (TOTAL) 70m A ORDERING INFORMATION DESCRIPTION...