P24C512F Datasheet | Puya Semiconductor

Description The P24C512F is I2C-patible Serial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 512 Kbits (64 Kbytes), which is organized in 128 bytes per page. Features - Single Supply Voltage and High Speed Mode - Minimum operating voltage down to 1.65V - 400k Hz/1MHz clock from 1.65 V to 3.6 V - 3.4MHz clock from 1.65 V to 3.6 V - Low power CMOS technology - Read current 0.2m A (400k Hz, typical) - Schmitt Trigger, Filtered Inputs for Noise Suppression - Transparent ECC on each group of four bytes which can correct 1 bit error - Write protect of the whole memory array - Additional write lockable page (Identification page) - Additional 128 bits Serial Number (Unique ID) - 128 bytes Page Write Modes, Partial Page Writes Allowed - Self-timed Write Cycle (5ms maximum) - High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years - HBM: 4 k V - Latch up Capability: +/- 200m A(25C) - Package: PDIP8, SOP8, TSSOP8, DFN8/UDFN8 and WLCSP8 1/27 1. Pin Configuration P24C512F Datasheet Rev.1.6 1.1 Pin Configuration Figure 1-1 Pin Configuration E0 E1 E2 Vss 4 8 VCC 7 WCB 6 SCL 5 SDA PDIP8/SOP8/TSSOP8/DFN8/UDFN8...