ICS95V847 Description
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ICS95V847 Key Features
- Low skew, low jitter PLL clock driver
- 1 to 5 differential clock distribution (SSTL_2)
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- CYCLE jitter: <60ps
- OUTPUT
- OUTPUT skew: <60ps
- Period jitter: ±30ps
- DUTY CYCLE: 49.5%