ICS95VLP857 Description
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ICS95VLP857 Key Features
- Lower power version than 95VLP857
- Low skew, low jitter PLL clock driver
- 1 to 10 differential clock distribution (SSTL_2)
- Feedback pins for input to output synchronization
- PD# for power management
- Spread Spectrum-tolerant inputs
- Auto PD when input signal removed
- Meets PC3200 Class A+ specification for DDR-I 400 support
- Covers all DDRI speed grades
- CYCLE jitter: <50ps