Description
- 72 Ld QFN, LVDS Mode
PIN NUMBER 1, 2, 17
9, 10, 19, 20, 21, 70, 71, 72 5, 8, 11, 14 27, 32, 62
26, 45, 61, 65 3 4
6, 7
LVDS PIN NAME DNC AVDD AVSS OVDD OVSS
NAPSLP VCM
VINBP, VINBN
LVDS PIN FUNCTION Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Powe
Features
- Single supply 1.8V operation.
- Clock duty cycle stabilizer.
- 75fs clock jitter.
- 700MHz bandwidth.
- Programmable built-in test patterns.
- Multi-ADC support
- SPI programmable fine gain and offset control - Support for multiple ADC synchronization - Optimized output timing.
- Nap and sleep modes - 200µs sleep wake-up time.
- Data output clock.
- DDR LVDS-compatible or LVCMOS outputs.
- Selectable clock divider
Applicati.
ISLA224P Datasheet
