Description
PIN NUMBER 2, 11, 14, 15, 46
12, 20, 47, 48 3, 6, 7, 10 4, 5 8, 9 1 44 16, 17 45 13
26, 29, 32, 35, 37, 38 25, 36, 39 22, 24 21, 23 18, 19 27, 28 30, 31 33, 34 40 41 42 43 PAD
NAME AVDD DNC AVSS BINP, BINN AINN, AINP VCM CLKDIV CLKP, CLKN NAPSLP RESETN OVSS OVDD OVDD (PLL) OVSS (PLL) SYNCP, SYNCN
Features
- including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. The ISLA224S is available in a space-saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C). Features.
- JESD204A/B High Speed Data Interface - JESD204A Compliant - JESD204B Device Subclass 0 Compliant - JESD204B Device.
ISLA224S Datasheet
