KAD5512HP Datasheet | Renesas

Features - Pin-patible with the KAD5512P Family, offering 2.2d B higher SNR - Programmable gain, offset and skew control - 950MHz analog input bandwidth - 60fs Clock jitter - Over-range indicator - Selectable clock divider: ÷1, ÷2 or ÷4 - Clock phase selection - Nap and sleep modes - Two’s plement, gray code or binary data format - DDR LVDS-patible or LVCMOS outputs - Programmable built-in test patterns - Single-supply 1.8V operation - Pb-free (Ro HS pliant) Applications - Power Amplifier linearization - Radar and satellite antenna array processing - Broadband munications - High-performance data acquisition - munications test equipment - Wi MAX and microwave receivers AVDD CLKDIV OVDD CLKP CLKN VINP VINN VCM CLOCK GENERATION 1.25V + - 12-BIT 250 MSPS SPI CONTROL DIGITAL ERROR CORRECTION LVDS/CMOS DRIVERS CLKOUTP CLKOUTN D[11:0]P D[11:0]N ORP ORN OUTFMT OUTMODE NAPSLP AVSS CSB SCLK SDIO SDO OVSS FN6808 Rev 4.00 May 31, 2016 FIGURE 1. BLOCK DIAGRAM Page 1 of...