KAD5512P-50 Datasheet | Renesas

Features - Programmable gain, offset and skew control - 1.3GHz analog input bandwidth - 60fs clock jitter - Over-range indicator - Selectable clock divider: ÷1 or ÷2 - Clock phase selection - Nap and sleep modes - Two’s plement, gray code or binary data format - DDR LVDS-patible or LVCMOS outputs - Programmable built-in test patterns - Single-supply 1.8V operation - Pb-free (Ro HS pliant) Applications - Radar and satellite antenna array processing - Broadband munications - High-performance data acquisition AVDD CLKDIV OVDD FN6805 Rev 4.00 May 31, 2016 CLKP CLKN VINP VINN VCM CLOCK GENERATION AND INTERLEAVE CONTROL CLKOUTP CLKOUTN SHA SHA 12-BIT 250 MSPS VREF DIGITAL ERROR CORRECTION 12-BIT 250 MSPS VREF 1.25V + - SPI CONTROL D[11:0]P D[11:0]N ORP ORN OUTFMT OUTMODE NAPSLP AGND RESETN CSB SCLK SDIO SDO...