KAD5512P Datasheet | Renesas

Features - Half the power of the pin-patible KAD5512HP family - 1.5GHz analog input bandwidth - 60fs clock jitter - Programmable gain, offset and skew control - Over-range indicator - Selectable clock divider: ÷1, ÷2 or ÷4 - Clock phase selection - Nap and sleep modes - Two’s plement, gray code or binary data format - SDR/DDR LVDS-patible or LVCMOS outputs - Programmable built-in test patterns - Single-supply 1.8V operation - Pb-free (Ro HS pliant) Applications - Power amplifier linearization - Radar and satellite antenna array processing - Broadband munications - High-performance data acquisition - munications test equipment - Wi MAX and microwave receivers AVDD CLKDIV OVDD CLKP CLKN VINP VINN CLOCK GENERATION CLKOUTP CLKOUTN 1.25V + - 12-BIT 250 MSPS ADC SPI CONTROL DIGITAL ERROR CORRECTION LVDS/CMOS DRIVERS D[11:0]P D[11:0]N ORP ORN OUTFMT OUTMODE NAPSLP AVSS CSB SCLK SDIO SDO OVSS FIGURE 1. BLOCK DIAGRAM FN6807 Rev 5.00 May 31, 2016 0 AIN = -1.0d BFS SNR = 66.0d...