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KAD5512P - 250/210/170/125MSPS ADC

Description

- 72 Ld QFN

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Features

  • Half the power of the pin-compatible KAD5512HP family.
  • 1.5GHz analog input bandwidth.
  • 60fs clock jitter.
  • Programmable gain, offset and skew control.
  • Over-range indicator.
  • Selectable clock divider: ÷1, ÷2 or ÷4.
  • Clock phase selection.
  • Nap and sleep modes.
  • Two’s complement, gray code or binary data format.
  • SDR/DDR LVDS-compatible or LVCMOS outputs.
  • Programmable built-in test patterns.
  • Singl.

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Datasheet preview – KAD5512P

Datasheet Details

Part number KAD5512P
Manufacturer Renesas
File Size 1.49 MB
Description 250/210/170/125MSPS ADC
Datasheet download datasheet KAD5512P Datasheet
Additional preview pages of the KAD5512P datasheet.

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Full PDF Text Transcription

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KAD5512P Low Power 12-Bit, 250/210/170/125MSPS ADC The KAD5512P is the low-power member of the KAD5512 family of 12-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5512P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A Serial Peripheral Interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P is available in 72 Ld and 48 Ld QFN packages with an exposed paddle. Operating from a 1.
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