Datasheet Details
| Part number | M5M5V5636UG-16 |
|---|---|
| Manufacturer | Renesas |
| File Size | 891.54 KB |
| Description | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| Datasheet |
 M5M5V5636UG-16 Datasheet
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General Description
The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit.
It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.
Key Features
- Fully registered inputs and outputs for pipelined operation.
- Fast clock speed: 167 and 133 MHz.
- Fast access time: 3.8 and 4.2 ns.
- Single 3.3V -5% and +5% power supply VDD.
- Separate VDDQ for 3.3V or 2.5V I/O.
- Single 2.5V -5% and +5% power supply VDD.
- Individual byte write (BWa# - BWd#) controls may be tied LOW.
- Single Read/Write control pin (W#).
- CKE# pin to enable clock and suspend operations.
- Internally s.